Modeling the Operation of Charge Trap Flash Memory-Part I: The Importance of Carrier Energy Relaxation

We present a novel approach to the modeling of carrier energy relaxation during high-field phases in semiconductor-oxide-nitride-oxide-semiconductor (SONOS) flash memory gate stacks. We show that this method integrates well with TCAD simulators and that taking the energy relaxation of carriers into...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2024-01, Vol.71 (1), p.547-553
Main Authors: Schanovsky, F., Verreck, D., Stanojevic, Z., Schallert, S., Arreghini, A., van den Bosch, G., Rosmeulen, M., Karner, M.
Format: Article
Language:English
Subjects:
Charge distribution
Charge trapping layer (CTL)
energy relaxation
flash
Flash memory (computers)
Incompatibility
incremental step pulse erase (ISPE)
incremental step pulse programming (ISPP)
Insulators
Logic gates
Mathematical models
Programming
Room temperature
semiconductor-oxide-nitride-oxide-semiconductor (SONOS)
Shape
Simulators
SONOS devices
TCAD
Tunneling
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Summary:We present a novel approach to the modeling of carrier energy relaxation during high-field phases in semiconductor-oxide-nitride-oxide-semiconductor (SONOS) flash memory gate stacks. We show that this method integrates well with TCAD simulators and that taking the energy relaxation of carriers into consideration solves two of the most prominent problems of trapping layer dynamics modeling: The missing slope degradation in incremental step-pulse programming (ISPP) simulations and the incompatibility of the resulting charge distributions with long-term room temperature charge retention measurements. This article consists of two parts where this part discusses the physical/TCAD level. The second part derives a semianalytical model specifically for programming that reduces the numerical complexity while still retaining the main physical assumptions and the applicability to experimental data.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2023.3339076