Advancing Monolayer 2-D nMOS and pMOS Transistor Integration From Growth to Van Der Waals Interface Engineering for Ultimate CMOS Scaling

2-D-material channels enable ultimate scaling of MOSFET transistors and will help Moore's Law scaling for years. We demonstrate the state of both n- and p-MOSFETs using monolayer transition metal dichalcogenide (TMD) channels of sub-1 nm thickness and manufacturable CVD, molecular beam epitaxy...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2021-12, Vol.68 (12), p.6592-6598
Main Authors: Dorow, Chelsey, O'Brien, Kevin, Naylor, Carl H., Lee, Sudarat, Penumatcha, Ashish, Hsiao, Andy, Tronic, Tristan, Christenson, Michael, Maxey, Kirby, Zhu, Hui, Oni, Adedapo, Alaan, Urusa, Gosavi, Tanay, Gupta, Arnab Sen, Bristol, Robert, Clendenning, Scott, Metz, Matthew, Avci, Uygar
Format: Article
Language:English
Subjects:
2-D CMOS
2-D transistor
Atomic layer epitaxy
Capacitance
Channels
Chemical vapor deposition
CMOS
Epitaxial growth
Fabrication
Hysteresis
Logic gates
Metals
Molecular beam epitaxy
Molybdenum disulfide
Monolayers
MOS devices
MOSFETs
Scaling
Semiconductor devices
Thickness measurement
Transistors
Transition metal compounds
transition metal dichalcogenide (TMD)
Tungsten disulfide
Two dimensional materials
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Summary:2-D-material channels enable ultimate scaling of MOSFET transistors and will help Moore's Law scaling for years. We demonstrate the state of both n- and p-MOSFETs using monolayer transition metal dichalcogenide (TMD) channels of sub-1 nm thickness and manufacturable CVD, molecular beam epitaxy (MBE), or seeded growth. nMOS devices on transferred MBE MoS 2 using novel contact metal show low variation, one of the lowest reported contact resistances ( {R}_{\text {c}} ) of 0.4 \text{k}\Omega \cdot \mu \text{m} , low hysteresis, and good subthreshold swing (SS) of 77 mV/dec. pMOS devices using CVD WSe 2 show 89 mV/dec SS, best reported for pMOS on grown films, but ON-current remains behind nMOS. We show {R}_{\text {C}} is improved by 5\times by using a bake process prior to contact metal deposition. Transfer-free, area-selective seeded growth techniques for WS 2 and MoS 2 are demonstrated as options for wafer-scale TMD channel growth. WS 2 transistors achieve 10 \mu \text{A}/\mu \text{m} ON-current, highest reported on WS 2 using seeded growth. A new capacitance method is shown to monitor 2-D material contact interface quality. Gate-oxide interface engineering through metal seeding and atomic layer deposition (ALD) demonstrates that a single 2-D channel material can selectively make pMOS or nMOS transistors, alike Si CMOS, and can also be used as a method to achieve p-type doping. We compare back-gated bare channel devices with dual-gate devices and observe hysteresis-free operation and an improvement in mobility with proper passivation.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2021.3118659