Multi- V UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage V T platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thicknes...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2011-08, Vol.58 (8), p.2473-2482
Main Authors: Noel, J-P, Thomas, O., Jaud, M., Weber, O., Poiroux, T., Fenouillet-Beranger, C., Rivallin, P., Scheiblin, P., Andrieu, F., Vinet, M., Rozeau, O., Boeuf, F., Faynot, O., Amara, A.
Format: Article
Language:English
Subjects:
Back plane (BP)
CMOS integrated circuits
Computer architecture
Doping
Logic gates
Microprocessors
MOS devices
multi- V_{T}
Silicon
ultra-thin body and buried oxide (BOX) FDSOI (UTBB FDSOI)
well implant
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Summary:This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage V T platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform that offers at least three distinct V T options (high- V T , standard- V T , and low- V T ). The multi- V T technology platform highlighted in this paper was developed with standard CMOS circuit design constraints in mind; its compatibility in terms of design and power management techniques, as well as its superior performance with regard to bulk CMOS, are described. Finally, it is shown that a multi- VT technology platform based on two gate materials offers additional advantages as a competitive solution. The proposed approach enables excellent channel electrostatic control and low VT variability of the FDSOI process. The viability of the proposed concept has been studied through technology computer-aided design simulations and demonstrated through experimental measurements on 30-nm gate length devices.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2011.2155658