High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware

Numerical linear algebra operations are key primitives in scientific computing. Performance optimizations of such operations have been extensively investigated. With the rapid advances in technology, hardware acceleration of linear algebra applications using FPGAs (field programmable gate arrays) ha...

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Bibliographic Details
Published in:IEEE transactions on computers 2008-08, Vol.57 (8), p.1057-1071
Main Authors: Ling Zhuo, Prasanna, V.K.
Format: Article
Language:English
Subjects:
Acceleration
Computations on matrices
Computer simulation
Devices
Field programmable gate arrays
Floating point arithmetic
Hardware
Linear algebra
Mathematical models
Multiplication
Parallel algorithms
Reconfigurable hardware
Studies
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Summary:Numerical linear algebra operations are key primitives in scientific computing. Performance optimizations of such operations have been extensively investigated. With the rapid advances in technology, hardware acceleration of linear algebra applications using FPGAs (field programmable gate arrays) has become feasible. In this paper, we propose FPGA-based designs for several basic linear algebra operations, including dot product, matrix-vector multiplication, matrix multiplication and matrix factorization. By identifying the parameters for each operation, we analyze the trade-offs and propose a high-performance design. In the implementations of the designs, the values of the parameters are determined according to the hardware constraints, such as the available chip area, the size of available memory, the memory bandwidth, and the number of I/O pins. The proposed designs are implemented on Xilinx Virtex-II Pro FPGAs. Experimental results show that our designs scale with the available hardware resources. Also, the performance of our designs compares favorably with that of general-purpose processor based designs. We also show that with faster floating-point units and larger devices, the performance of our designs increases accordingly.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2008.55