Theory and Demonstration of Noisy Oscillator Samplers for Clock Jitter and Phase Delay Measurement

A stochastic technique for on-chip measurement of jitter, delay, and duty-cycle of clock signals is introduced. The technique uses a simple noisy oscillator to perform random sampling and allows easy integration in CMOS process. Theoretical analysis proving the accuracy and robustness of the techniq...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2018-05, Vol.65 (5), p.1516-1528
Main Authors: Gantsog, Enkhbayasgalan, Apsel, Alyssa B.
Format: Article
Language:English
Subjects:
Clocks
CMOS
code density test
Delay
delay measurement
Delays
duty-cycle
Jitter
jitter measurement
Noise measurement
On-chip measurement
Oscillators
Random sampling
Samplers
Semiconductor device measurement
System-on-chip
Vibration
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Summary:A stochastic technique for on-chip measurement of jitter, delay, and duty-cycle of clock signals is introduced. The technique uses a simple noisy oscillator to perform random sampling and allows easy integration in CMOS process. Theoretical analysis proving the accuracy and robustness of the technique is presented. An implementation in CMOS 65nm process, occupying an active area of 0.015 mm 2 and consuming 0.89 mW, achieves a root mean square error of 0.1 and 0.31 ps in externally referenced and self-referenced jitter measurements, respectively.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2017.2758339