High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm

Non-binary low-density parity-check (NB-LDPC) codes are robust to various channel impairments. The excessive computational complexity and memory usage of the existing decoder designs are considerably expensive for practical applications. Based on a newly proposed simplified min-sum algorithm, which...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2012-11, Vol.59 (11), p.2784-2794
Main Authors: Chen, Xiaoheng, Wang, Chung-Li
Format: Article
Language:English
Subjects:
Algorithm design and analysis
Bit error rate
Complexity theory
Computer architecture
Decoder architecture
Decoding
error control coding
low-density parity-check (LDPC) codes
non-binary
Parity check codes
Throughput
VLSI design
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Non-binary low-density parity-check (NB-LDPC) codes are robust to various channel impairments. The excessive computational complexity and memory usage of the existing decoder designs are considerably expensive for practical applications. Based on a newly proposed simplified min-sum algorithm, which only has 0.05-0.1 dB performance loss against the sum-product algorithm, a highly efficient decoder architecture is developed. Compared with the existing works, our design has three advantages. First, the design increases the parallelism and throughput of the decoder by three to four times. The implementation results for the decoder show high throughput of 64 Mbps at 15 iterations. Second, this design saves memory usage by 38% to 76%. Third, this design shows 2.64 × area efficiency improvement even compared with the most state-of-the-art design.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2012.2190668