A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes

For an efficient multimode low-density parity-check (LDPC) decoder, most hardware resources, such as permutators, should be shared among different modes. Although an LDPC code constructed based on a Reed-Solomon (RS) code with two information symbols is not quasi-cyclic, in this paper, we reveal tha...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2010-10, Vol.57 (10), p.2790-2803
Main Authors: Ueng, Yeong-Luh, Yang, Chung-Jay, Wang, Kuan-Chieh, Chen, Chun-Jung
Format: Article
Language:English
Subjects:
Architecture
Circuits
Code standards
Codes
Communication standards
Computer science
Configurable
Decoders
Decoding
Delay
Design engineering
Frequency
Hardware
High rate
high throughput
Iterative decoding
Low density parity check codes
low-density parity-check (LDPC) codes
multimode
Parallel architectures
Parity check codes
Reed-Solomon (RS)-LDPC codes
shuffled iterative decoding
structured codes
Studies
Symbols
Throughput
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Summary:For an efficient multimode low-density parity-check (LDPC) decoder, most hardware resources, such as permutators, should be shared among different modes. Although an LDPC code constructed based on a Reed-Solomon (RS) code with two information symbols is not quasi-cyclic, in this paper, we reveal that the structural properties inherent in its parity-check matrix can be adopted in the design of configurable permutators. A partially parallel architecture combined with the proposed permutators is used to mitigate the increase in implementation complexity for the multimode function. The high check-node degree of a high-rate RS-LDPC code leads to challenges in the efficient implementation of a high-throughput decoder. To overcome this difficulty, the variable nodes have been partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and hence increase the maximum operating frequency. In addition, shuffled message-passing decoding is adopted, since fewer iterations can be used to achieve the desired bit-error-rate performance. In order to demonstrate the usefulness of the proposed flexible-permutator-based architecture, one single-mode rate-0.84 decoder and two multimode decoders whose code rates range between 0.79 and 0.93 have been implemented. These decoders can achieve multigigabit-per-second throughput. Using the proposed architecture to support lower rate RS-LDPC codes, e.g., rate-0.568 code, is also investigated.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2010.2046964