Optimization and Implementation of a Viterbi Decoder Under Flexibility Constraints

This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2008-09, Vol.55 (8), p.2411-2422
Main Authors: Kamuf, M., Owall, V., Anderson, J.B.
Format: Article
Language:English
Subjects:
Constraint optimization
Convolutional codes
Costs
Decoding
Degradation
Design optimization
Electrical Engineering, Electronic Engineering, Information Engineering
Elektroteknik och elektronik
Energy consumption
Engineering and Technology
flexibility
Hardware
Quantization
subset decoding
Teknik
Trellis-coded modulation (TCM)
Viterbi algorithm
Viterbi decoding
VLSI
wireless personal area network (WPAN)
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Summary:This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rate-flexible trellis datapath. A radix-2-based architecture for this datapath relaxes the hardware requirements on the branch metric and survivor path blocks substantially. The cost of flexibility in terms of cell area and power consumption is explored by an investigation of synthesized designs that provide different transmission rates. Two designs are fabricated in a digital 0.13-mum CMOS process. Based on post-layout simulations, a symbol baud rate of 168 Mbaud/s is achieved in TCM mode, equivalent to a maximum throughput of 840 Mbit/s using a 64-QAM constellation.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2008.918148