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4-Slot, 8-Drop Impedance-Matched Bidirectional Multidrop DQ Bus With a 4.8-Gb/s Memory Controller Transceiver

In this paper, we introduce an impedance-matched bidirectional multidrop (IMBM) DQ bus, together with a 4.8-Gb/s transceiver for a memory controller that supports this bus. Reflective ISI is eliminated at each stub of the IMBM DQ bus by resistive unidirectional impedance matching. A prototype memory...

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Bibliographic Details
Published in:IEEE transactions on components, packaging, and manufacturing technology (2011) packaging, and manufacturing technology (2011), 2013-05, Vol.3 (5), p.858-869
Main Authors: Shin, Woo-Yeol, Hong, Gi-Moon, Lee, Hyongmin, Han, Jae-Duk, Park, Kyu-Sang, Lim, Dong-Hyuk, Kim, Sunkwon, Shim, Daeyong, Chun, Jung-Hoon, Jeong, Deog-Kyoon, Kim, Suhwan
Format: Article
Language:English
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Summary:In this paper, we introduce an impedance-matched bidirectional multidrop (IMBM) DQ bus, together with a 4.8-Gb/s transceiver for a memory controller that supports this bus. Reflective ISI is eliminated at each stub of the IMBM DQ bus by resistive unidirectional impedance matching. A prototype memory controller transceiver is designed and fabricated in a 0.13-μm CMOS process and operates with a 1.2-V supply voltage. Its effectiveness is shown on various multidrop channel configurations. At 4.8 Gb/s, this transceiver with a 4-slot, 8-drop IMBM DQ bus has an eye opening of 0.39 UI in TX mode and 0.58 UI in RX mode, at a threshold of 10 -9 BER, whereas a comparable transceiver with a conventional 4-slot, 8-drop stub series terminated logic has no timing margin under the same test conditions. Our transceiver consumes 14.25 mW/Gb/s per DQ in TX mode, and 13.69 mW/Gb/s per DQ in RX mode.
ISSN:2156-3950
2156-3985
DOI:10.1109/TCPMT.2012.2231727