A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS

This paper presents an 8-channel energy-efficient analog front-end (AFE) for neural recording, with improvements in power supply rejection ratio (PSRR) and dynamic range. The input stage in the low noise amplifier (LNA) adopts low voltage supply (0.35 V) and current-reusing to achieve ultralow power...

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Bibliographic Details
Published in:IEEE transactions on biomedical circuits and systems 2020-08, Vol.14 (4), p.811-824
Main Authors: Lyu, Liangjian, Ye, Dawei, Shi, C.-J. Richard
Format: Article
Language:English
Subjects:
Active potential
Amplification
Amplifiers
Amplifiers, Electronic
analog front-end
Animals
averaged local field potential
Bias
Brain - physiology
Capacitors
CMOS
Dynamic range
Electrodes, Implanted
Electronics packaging
Electronics, Medical - instrumentation
Electrophysiological recording
Energy efficiency
Equipment Design
Gain
Impedance
local field potential
Low noise
low noise amplifier
low power
Low voltage
neural recorder
Neurons
Neurosciences - instrumentation
Noise levels
Power consumption
PSRR
Rats
Recording
Resistors
Semiconductors
Servomotors
Silicon - chemistry
Voltage
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Summary:This paper presents an 8-channel energy-efficient analog front-end (AFE) for neural recording, with improvements in power supply rejection ratio (PSRR) and dynamic range. The input stage in the low noise amplifier (LNA) adopts low voltage supply (0.35 V) and current-reusing to achieve ultralow power. To maintain a high PSRR performance while using such a low-voltage supply, a replica-biasing scheme is proposed to generate a stable bias current for the input stage of the LNA despite large supply interference. By exploiting the signal characteristics in the tetrode recording, an averaged local field potential (A-LFP) servo loop is introduced to extend the dynamic range without consuming too much extra power and chip area. The A-LFP signal is generated by integrating the four-channel PGA outputs from the same tetrode. Furthermore, the outputs of the programmable gain amplifier (PGA) are level shifted to bias the input nodes of the amplifier through large pseudo resistors, thus increase the maximum output range without distortion under the low-voltage supply. The proof-of-concept prototype is fabricated in a 65 nm CMOS process. Each recording channel including an LNA and a PGA occupies 0.04 mm^2 and consumes 340 nW from the 0.35 V and 0.7 V supply. Each A-LFP servo loop, which is shared by four recording channels, occupies 0.04 mm^2 and consumes 190 nW. The maximum gain of the AFE is 54 dB, and the input-referred noise is 6.7 \muV over the passband from 0.5 Hz to 6.5 kHz. Measurement also shows that the 0.35 V replica-biasing input stage can tolerate a large interferer up to 200 mVpp with a PSRR of 74 dB, which has been improved to 110 dB with a silicon respin that shields critical wires in the layout.
ISSN:1932-4545
1940-9990
DOI:10.1109/TBCAS.2020.2995566