Static Timing Analysis for Single-Flux-Quantum Circuits Composed of Various Gates

Superconductive single-flux-quantum (SFQ) circuits operate with very high clock frequency and its timing design is a difficult task. In circuit design, static timing analysis (STA) is a key process for evaluating and verifying the timing of a circuit design. Conventional timing analysis for SFQ circ...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on applied superconductivity 2022-08, Vol.32 (5), p.1-9
Main Authors: Kawaguchi, Takahiro, Takagi, Kazuyoshi, Takagi, Naofumi
Format: Article
Language:English
Subjects:
Approximation algorithms
Circuit design
Circuit synthesis
Circuits
Clockless logic gates
Clocks
common path pessimism removal (CPPR)
confluence buffer (CB)
Delays
Design analysis
Gates (circuits)
Logic circuits
Logic gates
nondestructive read-out (NDRO)
Pessimism
Pins
single-flux-quantum (SFQ) circuit
Static timing analysis
static timing analysis (STA)
Superconductors
Timing
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Superconductive single-flux-quantum (SFQ) circuits operate with very high clock frequency and its timing design is a difficult task. In circuit design, static timing analysis (STA) is a key process for evaluating and verifying the timing of a circuit design. Conventional timing analysis for SFQ circuits focuses on circuits composed of clocked gates and splitters; however, practical SFQ circuits are composed of various gates, i.e., not only clocked gates but also other gates, such as nondestructive read-out, confluence buffer, and clockless logic gates. In this article, to express timing constraints of both clocked gate cells and other cells, we define timing requirements of cells as minimum and maximum acceptable intervals on ordered pairs of input pins. Via these, we express timing constraints of cells in an SFQ circuit design. Furthermore, to eliminate unnecessary pessimism during variation-aware timing analysis, we propose a method of common path pessimism removal (CPPR) for SFQ circuits composed of various cells. We implement an STA tool using the defined timing constraints and the CPPR method. The experimental results show that our STA tool verifies the timing of SFQ circuits composed of various cells.
ISSN:1051-8223
1558-2515
DOI:10.1109/TASC.2022.3161052