Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps

Most TSVs are filled with copper; siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5 times 10 -6 /degC) is a few times higher than that of silicon (~2.5 times10 -6 /degC). Thus, when the copper filled through silicon via (TSV) is subjected to t...

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Bibliographic Details
Published in:IEEE transactions on advanced packaging 2009-11, Vol.32 (4), p.720-728
Main Authors: Selvanayagam, C.S., Lau, J.H., Xiaowu Zhang, Seah, S., Vaidyanathan, K., Chai, T.C.
Format: Article
Language:English
Subjects:
Applied sciences
Capacitive sensors
Chips
Copper
Design. Technologies. Operation analysis. Testing
Dielectrics
Electronics
Exact sciences and technology
Integrated circuits
Materials
Microelectronics
Microorganisms
modeling
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
Silicon
Silicon substrates
Strain
stress
Stresses
Temperature
Thermal expansion
Thermal loading
Thermal stresses
Through-silicon vias
Tungsten
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Summary:Most TSVs are filled with copper; siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5 times 10 -6 /degC) is a few times higher than that of silicon (~2.5 times10 -6 /degC). Thus, when the copper filled through silicon via (TSV) is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO 2 ), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this paper, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore's (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10 times 10 -6 /degC. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for 1) making a decision if underfill is necessary for the reliability of microbumps and 2) selecting underfill materials to minimize the stresses and strains in the microbumps.
ISSN:1521-3323
1557-9980
DOI:10.1109/TADVP.2009.2021661