Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro

This article presents a comprehensive assessment of the impact of various design assist techniques on the inherent performance and reliability of native resistive RAM (RRAM) on silicon. The collaborative optimization of design and technology plays a crucial role in replacing conventional flash memor...

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Published in:IEEE journal of solid-state circuits 2024-09, Vol.59 (9), p.3045-3057
Main Authors: Giraud, Bastien, Ricavy, Sebastien, Laffond, Cyrille, Sever, Ilan, Gherman, Valentin, Lepin, Florent, Diallo, Mariam, Zenati, Khadija, Dumas, Sylvain, Guille, Olivier, Vershkov, Maxim, Bricalli, Alessandro, Piccolboni, Giuseppe, Noel, Jean-Philippe, Samir, Anass, Pillonnet, Gael, Thonnart, Yvain, Molas, Gabriel
Format: Article
Language:English
Subjects:
Access time
Adaptive and reconfigurable systems
Algorithms
Bit error rate
Design analysis
Design optimization
Energy consumption
Error correction
error correction code (ECC)
Error correction codes
Error reduction
Flash memory (computers)
non-volatile memory
Power demand
Programming
Random access memory
Reliability
Resistors
Silicon
smart algorithm
variant-tolerant
Writing
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Summary:This article presents a comprehensive assessment of the impact of various design assist techniques on the inherent performance and reliability of native resistive RAM (RRAM) on silicon. The collaborative optimization of design and technology plays a crucial role in replacing conventional flash memory as the leading solution. We showcase that employing read-before-write, current-limitation, and write-termination techniques results in reductions of power consumption during programming operations by 47%, 56%, and 13%, respectively. Through their combination with write verification and error correction code mechanisms, these enhancements collectively achieve an 83% reduction in energy consumption and a notable 55% decrease in access time. These advancements are made possible by the introduction of a novel smart write algorithm (SWA). Leveraging a representative 128-kb RRAM macro implemented in 130-nm CMOS technology, this study significantly contributes to the feasible integration of RRAM for embedded applications. The experimental assessments on silicon validate the increased reliability, with a demonstrated 28.1- \mu \text{A} read margin after undergoing 1 million cycles without encountering any read errors, maintaining a bit error rate (BER) below 10-7.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2024.3386429