Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs

A novel architecture to implement quadrature voltage-controlled oscillators (QVCOs), based on the coupled phase-locked loop (CPLL) technique, is presented. The proposed solution allows to overcome the trade-off between low phase noise and small quadrature error, typical of conventional QVCOs. Both f...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2024-01, Vol.59 (1), p.1-13
Main Authors: Iesurum, Agata, Manente, Davide, Padovan, Fabio, Bassi, Matteo, Bevilacqua, Andrea
Format: Article
Language:English
Subjects:
CMOS
coupled phase-locked loop (CPLL)
Couplings
Error analysis
Figure of merit
Harmonic analysis
Mixers
Phase locked loops
Phase noise
quadrature voltage-controlled oscillator (QVCO)
Quadratures
radio frequency integrated circuits (RFIC)
Steady-state
Tuning
Voltage controlled oscillators
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Summary:A novel architecture to implement quadrature voltage-controlled oscillators (QVCOs), based on the coupled phase-locked loop (CPLL) technique, is presented. The proposed solution allows to overcome the trade-off between low phase noise and small quadrature error, typical of conventional QVCOs. Both figure-of-merit (FoM) can then be optimized simultaneously. Within the CPLL bandwidth, the QVCO phase noise is even improved by 3 dB with respect to the phase noise of the standalone free-running oscillators in the loop. Prototypes realized in a 28 nm bulk CMOS technology operate from 24 to 29.2 GHz (a 20% tuning range) and show a -134 dBc/Hz phase noise at 10 MHz offset from the 24 GHz carrier. The measured average quadrature error across the tuning range is 0.9^\circ . The QVCO dissipates 60 mW; its FoM is -184 dBc/Hz. The QVCO core area amounts to 0.2 mm ^2 .
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2023.3280360