A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays

An LO phase-shifting system based on digital fractional- N bang-bang phase-locked loops (PLLs) in the 8.5-10.0-GHz range is presented. A direct phase modulation method is leveraged to perform LO phase-shifting directly within the frequency synthesizer, leading to an inherently linear phase-shifting...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2023-09, Vol.58 (9), p.1-12
Main Authors: Tesolin, Francesco, Dartizio, Simone M., Buccoleri, Francesco, Santiccioli, Alessio, Bertulessi, Luca, Samori, Carlo, Lacaita, Andrea L., Levantino, Salvatore
Format: Article
Language:English
Subjects:
bang-bang phase detector (BBPD)
beamforming
digital-to-time converter (DTC)
DPLL
fractional-<inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> N</tex-math> </inline-formula>
Frequency dividers
frequency synthesizer
Frequency synthesizers
Integers
Linear phase
Linearity
LO phase-shifting
low-jitter
Mixers
multi-cores
multi-phase-locked loops (PLLs)
Phase error
Phase locked loops
Phase modulation
Phase noise
phased array
Phased arrays
PLL
Power demand
Radio frequency
Synchronism
Time synchronization
Transient analysis
Vibration
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Description
Summary:An LO phase-shifting system based on digital fractional- N bang-bang phase-locked loops (PLLs) in the 8.5-10.0-GHz range is presented. A direct phase modulation method is leveraged to perform LO phase-shifting directly within the frequency synthesizer, leading to an inherently linear phase-shifting characteristic, even in the presence of digital-to-time converter (DTC) nonlinearities. Synchronization between fractional- N PLL cores is achieved by clocking with the same reference clock the \Delta \Sigma modulator driving the frequency divider of each core. The adoption of a digital phase-offset correction technique canceling out timing skews greatly simplifies the reference-clock distribution and DTC matching. A dual-core prototype is implemented in a standard 28-nm CMOS process, where each element occupies 0.23-mm ^\text{2} area and dissipates 20-mW power. An arbitrary phase shift between the LO outputs can be set over the 360 ^\circ range with a resolution of 0.7 millidegree (19 bits). The rms phase accuracy is 0.76 ^\circ , and the peak-to-peak phase error is 2.1 ^\circ , without requiring any linearity or gain calibration. Each LO element features a - 58.7 dBc in-band fractional spur and a - 70 dBc reference spur, with a jitter versus power figure-of-merit of - 253.5 and - 250.0 dB for integer- N and fractional- N channels, respectively. The combined outputs of the two PLL cores reach an absolute jitter integrated from 1 kHz to 100 MHz (including spurs) of 38.2 and 59.78 fs, in integer- N and near-integer fractional- N operations, respectively.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2023.3272483