A 310-nA Quiescent Current 3-fs-FoM Fully Integrated Capacitorless Time-Domain LDO With Event-Driven Charge Pump and Feedforward Transient Enhancement

In this article, a fully integrated capacitorless low-dropout regulator (LDO) is presented for Internet-of-Things (IoT) edge sensor application. To achieve sub-1-V operation and fast transient response with low quiescent current, the conventional operational transconductance amplifier (OTA)-based er...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 2021-10, Vol.56 (10), p.2924-2933
Main Authors: Zhao, Jianming, Gao, Yuan, Zhang, Tan-Tan, Son, Hyunwoo, Heng, Chun-Huat
Format: Article
Language:English
Subjects:
Charge pump (CP)
Charge pumps
CMOS
Converters
Electric potential
Figure of merit
frequency comparator (FC)
Image edge detection
Internet of Things
low-dropout regulator (LDO)
Operational amplifiers
Optimization
Phase frequency detectors
Power consumption
Power semiconductor devices
Resistors
Signal processing
Time domain analysis
time-domain LDO
Time-frequency analysis
Transconductance
Transient response
Voltage
Voltage control
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this article, a fully integrated capacitorless low-dropout regulator (LDO) is presented for Internet-of-Things (IoT) edge sensor application. To achieve sub-1-V operation and fast transient response with low quiescent current, the conventional operational transconductance amplifier (OTA)-based error amplifier (EA) is replaced with oscillator-based voltage-to-time converter and time-domain signal processing, including time-domain edge-based frequency comparator (FC) and event-driven voltage mode charge pump (CP). Compared with the conventional phase frequency detector (PFD), the proposed clock-edge-based FC achieved more than six times power reduction. Event-driven CP is adopted to drive analog power transistor and the transient response is enhanced by feedforward capacitor C_{\mathrm {FD}} and coarse-fine CP control. To further reduce the power consumption, multi-voltage domain and clock frequency optimization are implemented. A prototype chip is fabricated in a standard 65-nm CMOS process. The design only consumes 310-nA quiescent current while achieving 0.5-1.2-V input range, 1.0\times 10^{6} load dynamic range, and 3-fs figure of merit (FoM).
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2021.3077453