A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques

A 5 Gb/s source-synchronous signaling system was developed utilizing a new clock/data skew minimization technique. The method incorporates a transmit clock delay line and integrating receiver yielding an increased tolerance to high frequency transmit source jitter. The system has the potential to su...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 2011-04, Vol.46 (4), p.974-985
Main Authors: Zerbe, J, Daly, B, Lei Luo, Stonecypher, W, Dettloff, W, Eble, J C, Stone, T, Jihong Ren, Leibowitz, B, Bucher, M, Satarzadeh, P, Qi Lin, Yue Lu, Kollipara, R
Format: Article
Language:English
Subjects:
Amplifiers
Applied sciences
Calibration
Circuit properties
Circuits of signal characteristics conditioning (including delay circuits)
Clocks
CMC
Common-mode clocking
Delay
Design. Technologies. Operation analysis. Testing
Devices
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
embedded clocking
Exact sciences and technology
Integrated circuits
integrating sampler
Jitter
Links
low power
matched source-synchronous
Minimization
MSSC
Performance measurement
Receivers
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Software
Swing
Synchronization
Tolerances
transceivers
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A 5 Gb/s source-synchronous signaling system was developed utilizing a new clock/data skew minimization technique. The method incorporates a transmit clock delay line and integrating receiver yielding an increased tolerance to high frequency transmit source jitter. The system has the potential to support rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second method to minimize clock distribution delays with embedded clocking via superposition of clock in the common-mode across two differential pairs was also explored. A test device was fabricated in TSMC's 40 nm LP CMOS process and performance measurements indicate substantial margin improvements, even when the matched source-synchronous system is subjected to realistic source SJ and independent PSIJ noise. Comparable performance was also achieved with embedded common-mode clocking with matched peak swings, indicating it as a potential solution for pin-constrained designs.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2011.2108120