A 90-nm Power Optimization Methodology With Application to the ARM 1136JF-S Microprocessor

An electrical and physical design power optimization methodology and design techniques developed to create an IC with an ARM 1136JF-S microprocessor in 90-nm standard CMOS are presented. Design technology and methodology enhancements to enable multiple supply voltage operation, leakage current and c...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2006-08, Vol.41 (8), p.1707-1717
Main Authors: Khan, A., Watson, P., Kuo, G., Le, D., Nguyen, T., Yang, S., Bennett, P., Pokai Huang, Gill, J., Hawkins, C., Goodenough, J., Demin Wang, Ahmed, I., Tran, P., Mak, H., Oanh Kim, Martin, F., Fan, Y., Ge, D., Kung, J., Shek, V.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit synthesis
Clocks
CMOS integrated circuits
CMOS technology
design automation
Design methodology
Design optimization
Design. Technologies. Operation analysis. Testing
digital systems
Electric potential
Electric power generation
Electric, optical and optoelectronic circuits
Electronics
electronics industry
Exact sciences and technology
General (including economical and industrial fields)
integrated circuit design
integrated circuit manufacture
Integrated circuits
Integrated circuits by function (including memories and processors)
Leakage
Leakage current
Methodology
Microprocessors
Optimization
Optimization methods
power distribution control
Reduction
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Standards development
Theoretical study. Circuits analysis and design
Voltage
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Description
Summary:An electrical and physical design power optimization methodology and design techniques developed to create an IC with an ARM 1136JF-S microprocessor in 90-nm standard CMOS are presented. Design technology and methodology enhancements to enable multiple supply voltage operation, leakage current and clock rate optimization, single-pass RTL synthesis, VDD selection, power optimization and timing and electrical closure in a multi-V DD domain design are described. A 40% reduction in dynamic and a 46% reduction in leakage power dissipation has been achieved while maintaining a 355-MHz operating clock rate under typical conditions. Functional and electrical design requirements were achieved with the first silicon
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2006.877248