Profiling interface traps in MOS transistors by the DC current-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peake...

Full description

Saved in:
Bibliographic Details
Published in:IEEE electron device letters 1996-02, Vol.17 (2), p.72-74
Main Authors: Chih-Tang Sah, Neugroschel, A., Han, K.M., Kavalieros, J.T.
Format: Article
Language:English
Subjects:
Charge carrier processes
Charge pumps
Current measurement
Density measurement
Electron traps
Leakage current
MOSFETs
Spontaneous emission
Stress measurement
Voltage
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 μm n-channel Si MOS transistor with about 10/sup 11/ traps/cm 2 generated by channel hot electron stress.
ISSN:0741-3106
1558-0563
DOI:10.1109/55.484127