Selective area growth of InP in shallow trench isolation on large scale Si(001) wafer using defect confinement technique

Heterogeneous integration of III–V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) subst...

Full description

Saved in:
Bibliographic Details
Published in:Journal of applied physics 2013-07, Vol.114 (3)
Main Authors: Merckling, C., Waldron, N., Jiang, S., Guo, W., Richard, O., Douhard, B., Moussa, A., Vanhaeren, D., Bender, H., Collaert, N., Heyns, M., Thean, A., Caymax, M., Vandervorst, W.
Format: Article
Language:English
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Heterogeneous integration of III–V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III–V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III–V virtual substrates on large-scale Si substrates.
ISSN:0021-8979
1089-7550
DOI:10.1063/1.4815959