Analysis of trap-assisted tunnelling in asymmetrical underlap 3D-cylindrical GAA-TFET based on hetero-spacer engineering for improved device reliability

A unique design for an asymmetrical underlap (AU) cylindrical-gate-all-around (GAA)-n-tunnel field effect transistor (TFET) based on hetero-spacer engineering with trap-assisted tunnelling (TAT) for reliability concern is proposed and validated. Here, DC and analogue performances such as ION, IOFF,...

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Bibliographic Details
Published in:Micro & nano letters 2017-12, Vol.12 (12), p.982-986
Main Authors: Beohar, Ankur, Yadav, Nandakishor, Vishvakarma, Santosh Kumar
Format: Article
Language:English
Subjects:
ambipolar behaviour suppression
analogue performance
asymmetrical underlap 3D‐cylindrical GAA‐TFET
AU cylindrical‐gate‐all‐around n‐tunnel field effect transistor
Design engineering
dielectric materials
Dielectrics
drain side spacer
drain‐channel junction
fast switching ON‐OFF transition
Field effect transistors
heterospacer dielectric engineering
high‐k dielectric spacer material
HS dielectric engineering
Leakage current
leakage currents
low‐k spacer dielectric
reliability
Reliability engineering
semiconductor device reliability
series resistance
source side spacer
source‐channel tunnelling junction
TAT analysis
trap‐assisted tunnelling analysis
tunnelling
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Summary:A unique design for an asymmetrical underlap (AU) cylindrical-gate-all-around (GAA)-n-tunnel field effect transistor (TFET) based on hetero-spacer engineering with trap-assisted tunnelling (TAT) for reliability concern is proposed and validated. Here, DC and analogue performances such as ION, IOFF, SS, ION/IOFF, Cgs, and Cgd have been investigated, while included TAT model and compared the examined device with AU GAA-TFET based on homo-spacer (HS) dielectric. On the basis of observation, the proposed device increases ON current as high as 2.1 × 10−6 A/µm, which corresponds to 1024 times improvement in ION/IOFF when compared with device based on HS. It also suppresses ambipolar behaviour with fast switching ON–OFF transition due to low leakage current (IOFF). These performances are mainly produced due to AU and low-k spacer dielectric which is replaced by high-k dielectric over source side spacer of the device, whereas drain side spacer is placed with high-k material along with increase in series resistance across drain–channel junction caused by drain underlap. Low-k spacer reduces the fringing field, and the depletion does not form at the source–gate edge, hence high source–channel tunnelling junction.
ISSN:1750-0443
1750-0443
DOI:10.1049/mnl.2017.0311