Design of optimised logic interface for network-on-chip architectures

Achievement of low power consumption in the field of network-on-chip (NoC) is a prominent research in recent days. Many works have attempted to improve performance in NoC using architectural and algorithmic models. The researches attempted to mitigate certain factors like power consumption, speed, c...

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Bibliographic Details
Published in:Electronics letters 2018-06, Vol.54 (12), p.744-746
Main Authors: Sakthivel, E, Arunraja, M, Uma, K.D, Shanthi, T, Muthukrishnan, A
Format: Article
Language:English
Subjects:
algorithmic models
amplifiers
architectural models
asynchronous NoC DTSA
circuit optimisation
Circuits and systems
conventional DTSA
double‐tail SAs
energy consumption
external sense amplifier
heavy traffic state
improved DTSAs
internal sense amplifier
logic design
low power consumption
low‐power electronics
network‐on‐chip
network‐on‐chip architectures
optimised logic interface design
real‐time data traffics
reconfigurable DTSA
R‐DTSA
size 90.0 nm
traffic estimators
traffic generators
transceivers
TSMC technology
variable energy aware SA link
V‐DTSA
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Summary:Achievement of low power consumption in the field of network-on-chip (NoC) is a prominent research in recent days. Many works have attempted to improve performance in NoC using architectural and algorithmic models. The researches attempted to mitigate certain factors like power consumption, speed, complexity, scalability, and flexibility. Currently, NoC engineers incorporated external or internal sense amplifier (SA) in the architectural model of NoC. In the conventional double-tail SAs (DTSAs), more amount of energy is consumed in the heavy traffic state. Hence, many improved DTSAs like reconfigurable DTSA (R-DTSA), variable energy aware SA link for asynchronous NoC (VELAN) DTSA (V-DTSA) were proposed in the previous works and employed with the transceivers. They were evaluated on TSMC 90 nm technology with the real-time data traffics which are obtained using traffic estimators and traffic generators. An optimised logic interface for transceivers of NoC which is superior to the conventional DTSA, R-DTSA, and V-DTSA is developed. The proposed design is implemented with transceivers and evaluated on TSMC 90 nm technology for comparing the performance with the previous SAs.
ISSN:0013-5194
1350-911X
1350-911X
DOI:10.1049/el.2018.0302