Optimal pipeline stage balancing in the presence of large isolated interconnect delay

Pipelining a combinational logic data-path without introducing pipeline stage delay imbalance is a key requirement for efficient digital processing. Balanced pipelining is easily achieved by simple logical effort optimisation when the interconnect and fan-out delay overhead is small and homogeneousl...

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Bibliographic Details
Published in:Electronics letters 2017-02, Vol.53 (4), p.229-231
Main Authors: Olivieri, M, Menichelli, F, Mastrandrea, A
Format: Article
Language:English
Subjects:
Architecture (computers)
Circuits and systems
combinational circuits
combinational logic data‐path
Delay
Digital
digital processing
Electronics
fan‐out delay overhead
heuristic approach
integrated circuit interconnections
Interconnections
large isolated interconnect delay
optimal pipeline stage balancing
optimisation
Optimization
pipeline processing
pipeline stage delay imbalance
Pipelines
Pipelining (computers)
simple logical effort optimisation
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Summary:Pipelining a combinational logic data-path without introducing pipeline stage delay imbalance is a key requirement for efficient digital processing. Balanced pipelining is easily achieved by simple logical effort optimisation when the interconnect and fan-out delay overhead is small and homogeneously distributed. When the target micro-architecture design includes isolated long interconnects, such as buses, optimal pipeline stage balancing becomes a tricky problem. This work formalises the solution based on the logical effort paradigm and evidences its advantage with respect to a heuristic approach.
ISSN:0013-5194
1350-911X
1350-911X
DOI:10.1049/el.2016.4262