Mobility Enhancement of Strained MoS 2 Transistor on Flat Substrate

Strain engineering has been proposed as a promising method to boost the carrier mobility of two-dimensional (2D) semiconductors. However, state-of-the-art straining approaches are largely based on putting 2D semiconductors on flexible substrates or rough substrate with nanostructures ( ., nanopartic...

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Bibliographic Details
Published in:ACS nano 2023-08, Vol.17 (15), p.14954-14962
Main Authors: Chen, Yang, Lu, Donglin, Kong, Lingan, Tao, Quanyang, Ma, Likuan, Liu, Liting, Lu, Zheyi, Li, Zhiwei, Wu, Ruixia, Duan, Xidong, Liao, Lei, Liu, Yuan
Format: Article
Language:English
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Summary:Strain engineering has been proposed as a promising method to boost the carrier mobility of two-dimensional (2D) semiconductors. However, state-of-the-art straining approaches are largely based on putting 2D semiconductors on flexible substrates or rough substrate with nanostructures ( ., nanoparticles, nanorods, ripples), where the observed mobility change is not only dependent on channel strain but could be impacted by the change of dielectric environment as well as rough interface scattering. Therefore, it remains an open question whether the pure lattice strain could improve the carrier mobilities of 2D semiconductors, limiting the achievement of high-performance 2D transistors. Here, we report a strain engineering approach to fabricate highly strained MoS transistors on a flat substrate. By mechanically laminating a prefabricated MoS transistor onto a custom-designed trench structure on flat substrate, well-controlled strain can be uniformly generated across the 2D channel. In the meantime, the substrate and the back-gate dielectric layer remain flat without any roughness-induced scattering effect or variation of the dielectric environment. Based on this technique, we demonstrate the MoS electron mobility could be enhanced by tension strain and decreased by compression strain, consistent with theoretical predictions. The highest mobility enhancement is 152% for monolayer MoS and 64% for bilayer MoS transistors, comparable to that of a silicon device. Our method not only provides a compatible approach to uniformly strain the layered semiconductors on flat and solid substrate but also demonstrates an effective method to boost the carrier mobilities of 2D transistors.
ISSN:1936-0851
1936-086X
DOI:10.1021/acsnano.3c03626