Loading…
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience
•Our RAP model enables systematic CMOS fault abstraction and error propagation.•RAP assumes that physically induced faults eventually manifest as bit flips.•Higher layer error models can be derived from probabilistic bit flip functions.•SoC designers can optimize system resilience across multiple ab...
Saved in:
| Published in: | Microelectronics and reliability 2014-06, Vol.54 (6-7), p.1066-1074 |
|---|---|
| Main Authors: | , , , , , , , , , , , , , , , , , , , |
| Format: | Article |
| Language: | English |
| Subjects: | |
| Citations: | Items that this one cites Items that cite this one |
| Online Access: | Get full text |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| cited_by | cdi_FETCH-LOGICAL-c393t-7e12b7e4d63461ff036cc8f98829a8f794002c565bbb413363ef380bb67f57613 |
|---|---|
| cites | cdi_FETCH-LOGICAL-c393t-7e12b7e4d63461ff036cc8f98829a8f794002c565bbb413363ef380bb67f57613 |
| container_end_page | 1074 |
| container_issue | 6-7 |
| container_start_page | 1066 |
| container_title | Microelectronics and reliability |
| container_volume | 54 |
| creator | Herkersdorf, Andreas Aliee, Hananeh Engel, Michael Glaß, Michael Gimmler-Dumont, Christina Henkel, Jörg Kleeberger, Veit B. Kochte, Michael A. Kühn, Johannes M. Mueller-Gritschneder, Daniel Nassif, Sani R. Rauchfuss, Holm Rosenstiel, Wolfgang Schlichtmann, Ulf Shafique, Muhammad Tahoori, Mehdi B. Teich, Jürgen Wehn, Norbert Weis, Christian Wunderlich, Hans-Joachim |
| description | •Our RAP model enables systematic CMOS fault abstraction and error propagation.•RAP assumes that physically induced faults eventually manifest as bit flips.•Higher layer error models can be derived from probabilistic bit flip functions.•SoC designers can optimize system resilience across multiple abstraction levels.•Real-world case studies with SRAM soft-errors in CPU cache and MIMO detector are shown.
The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods. |
| doi_str_mv | 10.1016/j.microrel.2013.12.012 |
| format | article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_1671606273</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><els_id>S0026271413004630</els_id><sourcerecordid>1671606273</sourcerecordid><originalsourceid>FETCH-LOGICAL-c393t-7e12b7e4d63461ff036cc8f98829a8f794002c565bbb413363ef380bb67f57613</originalsourceid><addsrcrecordid>eNqFkMFqGzEURUVJoY7TXyhaOouZ6EljaaarGpM0hUCMaSA7MaN5SmRmJEeSC_77jOu2267e5t77OIeQL8BKYCBvduXoTAwRh5IzECXwkgH_QGZQK140FTxfkBljXBZcQfWJXKa0Y4wpBjAjYYvJDQ69QbqK2ZnD0GYXPN0E5zNdbFeb6690HUNKxdAeMdIe9-j7tpta-UjH0OPg_Au1IVLf-jBinkLpmDKORfCFeXV7Gv89uSIfbTsk_PznzsnT3e3P9X3x8Pj9x3r1UBjRiFwoBN4prHopKgnWMiGNqW1T17xpa6uaagIyS7nsuq4CIaRAK2rWdVLZpZIg5mRx3t3H8HbAlPXoksFhaD2GQ9IgFUgmuRJTVJ6j5kQZ0ep9dGMbjxqYPhnWO_3XsD4Z1sD1ZHgqfjsXcQL55TDqZH5D9i6iyboP7n8T7_9oiSI</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1671606273</pqid></control><display><type>article</type><title>Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience</title><source>ScienceDirect Freedom Collection</source><creator>Herkersdorf, Andreas ; Aliee, Hananeh ; Engel, Michael ; Glaß, Michael ; Gimmler-Dumont, Christina ; Henkel, Jörg ; Kleeberger, Veit B. ; Kochte, Michael A. ; Kühn, Johannes M. ; Mueller-Gritschneder, Daniel ; Nassif, Sani R. ; Rauchfuss, Holm ; Rosenstiel, Wolfgang ; Schlichtmann, Ulf ; Shafique, Muhammad ; Tahoori, Mehdi B. ; Teich, Jürgen ; Wehn, Norbert ; Weis, Christian ; Wunderlich, Hans-Joachim</creator><creatorcontrib>Herkersdorf, Andreas ; Aliee, Hananeh ; Engel, Michael ; Glaß, Michael ; Gimmler-Dumont, Christina ; Henkel, Jörg ; Kleeberger, Veit B. ; Kochte, Michael A. ; Kühn, Johannes M. ; Mueller-Gritschneder, Daniel ; Nassif, Sani R. ; Rauchfuss, Holm ; Rosenstiel, Wolfgang ; Schlichtmann, Ulf ; Shafique, Muhammad ; Tahoori, Mehdi B. ; Teich, Jürgen ; Wehn, Norbert ; Weis, Christian ; Wunderlich, Hans-Joachim</creatorcontrib><description>•Our RAP model enables systematic CMOS fault abstraction and error propagation.•RAP assumes that physically induced faults eventually manifest as bit flips.•Higher layer error models can be derived from probabilistic bit flip functions.•SoC designers can optimize system resilience across multiple abstraction levels.•Real-world case studies with SRAM soft-errors in CPU cache and MIMO detector are shown.
The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.</description><identifier>ISSN: 0026-2714</identifier><identifier>EISSN: 1872-941X</identifier><identifier>DOI: 10.1016/j.microrel.2013.12.012</identifier><language>eng</language><publisher>Elsevier Ltd</publisher><subject>Computer programs ; Design engineering ; Error functions ; Mathematical models ; Probabilistic methods ; Probability theory ; Resilience ; Software</subject><ispartof>Microelectronics and reliability, 2014-06, Vol.54 (6-7), p.1066-1074</ispartof><rights>2014 Elsevier Ltd</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c393t-7e12b7e4d63461ff036cc8f98829a8f794002c565bbb413363ef380bb67f57613</citedby><cites>FETCH-LOGICAL-c393t-7e12b7e4d63461ff036cc8f98829a8f794002c565bbb413363ef380bb67f57613</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>315,786,790,27957,27958</link.rule.ids></links><search><creatorcontrib>Herkersdorf, Andreas</creatorcontrib><creatorcontrib>Aliee, Hananeh</creatorcontrib><creatorcontrib>Engel, Michael</creatorcontrib><creatorcontrib>Glaß, Michael</creatorcontrib><creatorcontrib>Gimmler-Dumont, Christina</creatorcontrib><creatorcontrib>Henkel, Jörg</creatorcontrib><creatorcontrib>Kleeberger, Veit B.</creatorcontrib><creatorcontrib>Kochte, Michael A.</creatorcontrib><creatorcontrib>Kühn, Johannes M.</creatorcontrib><creatorcontrib>Mueller-Gritschneder, Daniel</creatorcontrib><creatorcontrib>Nassif, Sani R.</creatorcontrib><creatorcontrib>Rauchfuss, Holm</creatorcontrib><creatorcontrib>Rosenstiel, Wolfgang</creatorcontrib><creatorcontrib>Schlichtmann, Ulf</creatorcontrib><creatorcontrib>Shafique, Muhammad</creatorcontrib><creatorcontrib>Tahoori, Mehdi B.</creatorcontrib><creatorcontrib>Teich, Jürgen</creatorcontrib><creatorcontrib>Wehn, Norbert</creatorcontrib><creatorcontrib>Weis, Christian</creatorcontrib><creatorcontrib>Wunderlich, Hans-Joachim</creatorcontrib><title>Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience</title><title>Microelectronics and reliability</title><description>•Our RAP model enables systematic CMOS fault abstraction and error propagation.•RAP assumes that physically induced faults eventually manifest as bit flips.•Higher layer error models can be derived from probabilistic bit flip functions.•SoC designers can optimize system resilience across multiple abstraction levels.•Real-world case studies with SRAM soft-errors in CPU cache and MIMO detector are shown.
The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.</description><subject>Computer programs</subject><subject>Design engineering</subject><subject>Error functions</subject><subject>Mathematical models</subject><subject>Probabilistic methods</subject><subject>Probability theory</subject><subject>Resilience</subject><subject>Software</subject><issn>0026-2714</issn><issn>1872-941X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><recordid>eNqFkMFqGzEURUVJoY7TXyhaOouZ6EljaaarGpM0hUCMaSA7MaN5SmRmJEeSC_77jOu2267e5t77OIeQL8BKYCBvduXoTAwRh5IzECXwkgH_QGZQK140FTxfkBljXBZcQfWJXKa0Y4wpBjAjYYvJDQ69QbqK2ZnD0GYXPN0E5zNdbFeb6690HUNKxdAeMdIe9-j7tpta-UjH0OPg_Au1IVLf-jBinkLpmDKORfCFeXV7Gv89uSIfbTsk_PznzsnT3e3P9X3x8Pj9x3r1UBjRiFwoBN4prHopKgnWMiGNqW1T17xpa6uaagIyS7nsuq4CIaRAK2rWdVLZpZIg5mRx3t3H8HbAlPXoksFhaD2GQ9IgFUgmuRJTVJ6j5kQZ0ep9dGMbjxqYPhnWO_3XsD4Z1sD1ZHgqfjsXcQL55TDqZH5D9i6iyboP7n8T7_9oiSI</recordid><startdate>20140601</startdate><enddate>20140601</enddate><creator>Herkersdorf, Andreas</creator><creator>Aliee, Hananeh</creator><creator>Engel, Michael</creator><creator>Glaß, Michael</creator><creator>Gimmler-Dumont, Christina</creator><creator>Henkel, Jörg</creator><creator>Kleeberger, Veit B.</creator><creator>Kochte, Michael A.</creator><creator>Kühn, Johannes M.</creator><creator>Mueller-Gritschneder, Daniel</creator><creator>Nassif, Sani R.</creator><creator>Rauchfuss, Holm</creator><creator>Rosenstiel, Wolfgang</creator><creator>Schlichtmann, Ulf</creator><creator>Shafique, Muhammad</creator><creator>Tahoori, Mehdi B.</creator><creator>Teich, Jürgen</creator><creator>Wehn, Norbert</creator><creator>Weis, Christian</creator><creator>Wunderlich, Hans-Joachim</creator><general>Elsevier Ltd</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20140601</creationdate><title>Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience</title><author>Herkersdorf, Andreas ; Aliee, Hananeh ; Engel, Michael ; Glaß, Michael ; Gimmler-Dumont, Christina ; Henkel, Jörg ; Kleeberger, Veit B. ; Kochte, Michael A. ; Kühn, Johannes M. ; Mueller-Gritschneder, Daniel ; Nassif, Sani R. ; Rauchfuss, Holm ; Rosenstiel, Wolfgang ; Schlichtmann, Ulf ; Shafique, Muhammad ; Tahoori, Mehdi B. ; Teich, Jürgen ; Wehn, Norbert ; Weis, Christian ; Wunderlich, Hans-Joachim</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c393t-7e12b7e4d63461ff036cc8f98829a8f794002c565bbb413363ef380bb67f57613</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2014</creationdate><topic>Computer programs</topic><topic>Design engineering</topic><topic>Error functions</topic><topic>Mathematical models</topic><topic>Probabilistic methods</topic><topic>Probability theory</topic><topic>Resilience</topic><topic>Software</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Herkersdorf, Andreas</creatorcontrib><creatorcontrib>Aliee, Hananeh</creatorcontrib><creatorcontrib>Engel, Michael</creatorcontrib><creatorcontrib>Glaß, Michael</creatorcontrib><creatorcontrib>Gimmler-Dumont, Christina</creatorcontrib><creatorcontrib>Henkel, Jörg</creatorcontrib><creatorcontrib>Kleeberger, Veit B.</creatorcontrib><creatorcontrib>Kochte, Michael A.</creatorcontrib><creatorcontrib>Kühn, Johannes M.</creatorcontrib><creatorcontrib>Mueller-Gritschneder, Daniel</creatorcontrib><creatorcontrib>Nassif, Sani R.</creatorcontrib><creatorcontrib>Rauchfuss, Holm</creatorcontrib><creatorcontrib>Rosenstiel, Wolfgang</creatorcontrib><creatorcontrib>Schlichtmann, Ulf</creatorcontrib><creatorcontrib>Shafique, Muhammad</creatorcontrib><creatorcontrib>Tahoori, Mehdi B.</creatorcontrib><creatorcontrib>Teich, Jürgen</creatorcontrib><creatorcontrib>Wehn, Norbert</creatorcontrib><creatorcontrib>Weis, Christian</creatorcontrib><creatorcontrib>Wunderlich, Hans-Joachim</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Microelectronics and reliability</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Herkersdorf, Andreas</au><au>Aliee, Hananeh</au><au>Engel, Michael</au><au>Glaß, Michael</au><au>Gimmler-Dumont, Christina</au><au>Henkel, Jörg</au><au>Kleeberger, Veit B.</au><au>Kochte, Michael A.</au><au>Kühn, Johannes M.</au><au>Mueller-Gritschneder, Daniel</au><au>Nassif, Sani R.</au><au>Rauchfuss, Holm</au><au>Rosenstiel, Wolfgang</au><au>Schlichtmann, Ulf</au><au>Shafique, Muhammad</au><au>Tahoori, Mehdi B.</au><au>Teich, Jürgen</au><au>Wehn, Norbert</au><au>Weis, Christian</au><au>Wunderlich, Hans-Joachim</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience</atitle><jtitle>Microelectronics and reliability</jtitle><date>2014-06-01</date><risdate>2014</risdate><volume>54</volume><issue>6-7</issue><spage>1066</spage><epage>1074</epage><pages>1066-1074</pages><issn>0026-2714</issn><eissn>1872-941X</eissn><notes>ObjectType-Article-1</notes><notes>SourceType-Scholarly Journals-1</notes><notes>ObjectType-Feature-2</notes><notes>content type line 23</notes><abstract>•Our RAP model enables systematic CMOS fault abstraction and error propagation.•RAP assumes that physically induced faults eventually manifest as bit flips.•Higher layer error models can be derived from probabilistic bit flip functions.•SoC designers can optimize system resilience across multiple abstraction levels.•Real-world case studies with SRAM soft-errors in CPU cache and MIMO detector are shown.
The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.</abstract><pub>Elsevier Ltd</pub><doi>10.1016/j.microrel.2013.12.012</doi><tpages>9</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0026-2714 |
| ispartof | Microelectronics and reliability, 2014-06, Vol.54 (6-7), p.1066-1074 |
| issn | 0026-2714 1872-941X |
| language | eng |
| recordid | cdi_proquest_miscellaneous_1671606273 |
| source | ScienceDirect Freedom Collection |
| subjects | Computer programs Design engineering Error functions Mathematical models Probabilistic methods Probability theory Resilience Software |
| title | Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-09-22T05%3A28%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Resilience%20Articulation%20Point%20(RAP):%20Cross-layer%20dependability%20modeling%20for%20nanometer%20system-on-chip%20resilience&rft.jtitle=Microelectronics%20and%20reliability&rft.au=Herkersdorf,%20Andreas&rft.date=2014-06-01&rft.volume=54&rft.issue=6-7&rft.spage=1066&rft.epage=1074&rft.pages=1066-1074&rft.issn=0026-2714&rft.eissn=1872-941X&rft_id=info:doi/10.1016/j.microrel.2013.12.012&rft_dat=%3Cproquest_cross%3E1671606273%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c393t-7e12b7e4d63461ff036cc8f98829a8f794002c565bbb413363ef380bb67f57613%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=1671606273&rft_id=info:pmid/&rfr_iscdi=true |