Twin binary sequences: a nonredundant representation for general nonslicing floorplan

The efficiency and effectiveness of many floorplanning methods depend very much on the representation of the geometrical relationship between the modules. A good representation can shorten the searching process so that more accurate estimations on area and interconnect costs can be performed. Nonsli...

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Published in:	IEEE transactions on computer-aided design of integrated circuits and systems 2003-04, Vol.22 (4), p.457-469
Main Authors:	Young, E.F.Y., Chu, C.C.N., Shen, Z.C.
Format:	Article
Language:	eng
Subjects:	Binary sequences Circuit optimization Computer science Costs Delay Design engineering Design optimization Floorplans Insertion Inserts Integrated circuit interconnections Minimization Modules Mosaics Representations Shape Solution space Studies Very large scale integration
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title	Twin binary sequences: a nonredundant representation for general nonslicing floorplan
format	Article
creator	Young, E.F.Y. Chu, C.C.N. Shen, Z.C.
subjects	Binary sequences Circuit optimization Computer science Costs Delay Design engineering Design optimization Floorplans Insertion Inserts Integrated circuit interconnections Minimization Modules Mosaics Representations Shape Solution space Studies Very large scale integration
ispartof	IEEE transactions on computer-aided design of integrated circuits and systems, 2003-04, Vol.22 (4), p.457-469
description	The efficiency and effectiveness of many floorplanning methods depend very much on the representation of the geometrical relationship between the modules. A good representation can shorten the searching process so that more accurate estimations on area and interconnect costs can be performed. Nonslicing floorplan is the most general kind of floorplan that is commonly used. Unfortunately, there is not yet any complete and nonredundant topological representation for nonslicing structure. In this paper, we propose the first representation of this kind. Like some previous work (Zhou et al. 2001), we have also made use of a mosaic floorplan as an intermediate step. However, instead of including a more than sufficient number of extra dummy blocks in the set of modules (that will increase the size of the solution space significantly), our representation allows us to insert an exact number of irreducible empty rooms to a mosaic floorplan such that every nonslicing floorplan can be obtained uniquely from one and only one mosaic floorplan. The size of the solution space is only O(n!2/sup 3n//n/sup 1.5/), which is the size without empty room insertion, but every nonslicing floorplan can be generated uniquely and efficiently in linear time without any redundant representation.
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source	IEEE Electronic Library (IEL) Journals
identifier	ISSN: 0278-0070
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issn	0278-0070 1937-4151
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A good representation can shorten the searching process so that more accurate estimations on area and interconnect costs can be performed. Nonslicing floorplan is the most general kind of floorplan that is commonly used. Unfortunately, there is not yet any complete and nonredundant topological representation for nonslicing structure. In this paper, we propose the first representation of this kind. Like some previous work (Zhou et al. 2001), we have also made use of a mosaic floorplan as an intermediate step. However, instead of including a more than sufficient number of extra dummy blocks in the set of modules (that will increase the size of the solution space significantly), our representation allows us to insert an exact number of irreducible empty rooms to a mosaic floorplan such that every nonslicing floorplan can be obtained uniquely from one and only one mosaic floorplan. The size of the solution space is only O(n!2/sup 3n//n/sup 1.5/), which is the size without empty room insertion, but every nonslicing floorplan can be generated uniquely and efficiently in linear time without any redundant representation.</description><subject>Binary sequences</subject><subject>Circuit optimization</subject><subject>Computer science</subject><subject>Costs</subject><subject>Delay</subject><subject>Design engineering</subject><subject>Design optimization</subject><subject>Floorplans</subject><subject>Insertion</subject><subject>Inserts</subject><subject>Integrated circuit interconnections</subject><subject>Minimization</subject><subject>Modules</subject><subject>Mosaics</subject><subject>Representations</subject><subject>Shape</subject><subject>Solution space</subject><subject>Studies</subject><subject>Very large scale integration</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2003</creationdate><recordtype>article</recordtype><recordid>eNpdkM9LwzAYhoMoOKd3wUvx4qnz-5K2abyN-RMGXuY5ZM3X0dElNekQ_3tbKgie3svzvrw8jF0jLBBB3W9Wy8cFBxCLElSR4wmboRIyzTDHUzYDLssUQMI5u4hxD4BZztWMfWy-GpdsG2fCdxLp80iuoviQmMR5F8genTWuTwJ1gSK53vSNd0ntQ7IjR8G0IxfbpmrcLqlb70PXGnfJzmrTRrr6zTnbPD9tVq_p-v3lbbVcp5Xg0Kc1lIIbtNYYa0UpRWmxrrdFhoXNgfKqKLYFmpzAZoiZhBq5tJJQqTLjuZizu2m2C354Hnt9aGJF7fCA_DFqBSiBY4EDefuP3PtjcMM3XQ5TUhZcDhBMUBV8jIFq3YXmMIjRCHqUrEfJepSsJ8lD5WaqNET0h6MCVQrxAxXxeH8</recordid><startdate>20030401</startdate><enddate>20030401</enddate><creator>Young, E.F.Y.</creator><creator>Chu, C.C.N.</creator><creator>Shen, Z.C.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20030401</creationdate><title>Twin binary sequences: a nonredundant representation for general nonslicing floorplan</title><author>Young, E.F.Y. ; Chu, C.C.N. ; Shen, Z.C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c320t-f0832a1ddaadd38738d1ffb6416d50e5c66b61a5e0d411470f127d7e19984253</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Binary sequences</topic><topic>Circuit optimization</topic><topic>Computer science</topic><topic>Costs</topic><topic>Delay</topic><topic>Design engineering</topic><topic>Design optimization</topic><topic>Floorplans</topic><topic>Insertion</topic><topic>Inserts</topic><topic>Integrated circuit interconnections</topic><topic>Minimization</topic><topic>Modules</topic><topic>Mosaics</topic><topic>Representations</topic><topic>Shape</topic><topic>Solution space</topic><topic>Studies</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Young, E.F.Y.</creatorcontrib><creatorcontrib>Chu, C.C.N.</creatorcontrib><creatorcontrib>Shen, Z.C.</creatorcontrib><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Young, E.F.Y.</au><au>Chu, C.C.N.</au><au>Shen, Z.C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Twin binary sequences: a nonredundant representation for general nonslicing floorplan</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>2003-04-01</date><risdate>2003</risdate><volume>22</volume><issue>4</issue><spage>457</spage><epage>469</epage><pages>457-469</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><notes>ObjectType-Article-2</notes><notes>SourceType-Scholarly Journals-1</notes><notes>ObjectType-Feature-1</notes><notes>content type line 23</notes><abstract>The efficiency and effectiveness of many floorplanning methods depend very much on the representation of the geometrical relationship between the modules. A good representation can shorten the searching process so that more accurate estimations on area and interconnect costs can be performed. Nonslicing floorplan is the most general kind of floorplan that is commonly used. Unfortunately, there is not yet any complete and nonredundant topological representation for nonslicing structure. In this paper, we propose the first representation of this kind. Like some previous work (Zhou et al. 2001), we have also made use of a mosaic floorplan as an intermediate step. However, instead of including a more than sufficient number of extra dummy blocks in the set of modules (that will increase the size of the solution space significantly), our representation allows us to insert an exact number of irreducible empty rooms to a mosaic floorplan such that every nonslicing floorplan can be obtained uniquely from one and only one mosaic floorplan. The size of the solution space is only O(n!2/sup 3n//n/sup 1.5/), which is the size without empty room insertion, but every nonslicing floorplan can be generated uniquely and efficiently in linear time without any redundant representation.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCAD.2003.809651</doi><oa>free_for_read</oa></addata></record>