Technology Assessment of Through-Silicon Via by Using C- V and C- t Measurements

C-V characteristics of through-silicon vias (TSVs) manufactured in two different processing lines are compared to demonstrate the reproducibility of the TSV process module in terms of the minimum TSV depletion capacitance in the operating voltage region. TSV C-V and C-t measurements before and after...

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Bibliographic Details
Published in:IEEE electron device letters 2011-07, Vol.32 (7), p.946-948
Main Authors: Katti, G., Stucchi, M., Velenis, D., Thangaraju, S., De Meyer, K., Dehaene, W., Beyne, E.
Format: Article
Language:English
Subjects:
3-D ICs
Applied sciences
C - V and C - t measurements
Capacitance
Copper
Depletion
Design. Technologies. Operation analysis. Testing
Devices
Electric potential
Electronics
Exact sciences and technology
Integrated circuits
Integrity
Oxides
Reproducibility
Semiconductor device measurement
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon
Stress
Temperature measurement
Thermal cycling
through-silicon via (TSV)
Through-silicon vias
TSV reproducibility
Voltage
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Summary:C-V characteristics of through-silicon vias (TSVs) manufactured in two different processing lines are compared to demonstrate the reproducibility of the TSV process module in terms of the minimum TSV depletion capacitance in the operating voltage region. TSV C-V and C-t measurements before and after thermocycling are employed for assessing the oxide liner and Ta barrier integrity of the TSV under the influence of temperature. It is observed that TSV C-V and C-t characteristics remain unchanged before and after thermocycling (1000 cycles).
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2011.2141650