Metastability behavior of mismatched CMOS flip-flops using state diagram analysis

The effect on the metastability of the mismatch of FET parameters and load capacitances in a CMOS latch/flip-flop is analyzed. A novel method using state diagrams is proposed. On the state diagrams obtained by transient analysis of the latch, a straight line can be approximately drawn that defines t...

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Main Authors: van Noije, W.A.M., Liu, W.T., Navarro, J.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Circuit simulation
Clocks
FETs
Flip-flops
Inverters
Latches
Metastasis
Very large scale integration
Voltage
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creator van Noije, W.A.M.
Liu, W.T.
Navarro, J.
description The effect on the metastability of the mismatch of FET parameters and load capacitances in a CMOS latch/flip-flop is analyzed. A novel method using state diagrams is proposed. On the state diagrams obtained by transient analysis of the latch, a straight line can be approximately drawn that defines two semiplanes, which precisely determine the latch final state. SPICE simulation results are shown for matched/mismatched flip-flops.
doi_str_mv 10.1109/CICC.1993.590809
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Capacitance
Circuit simulation
Clocks
FETs
Flip-flops
Inverters
Latches
Metastasis
Very large scale integration
Voltage
title Metastability behavior of mismatched CMOS flip-flops using state diagram analysis
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