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A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) gra...

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Published in:	IEEE journal of solid-state circuits 1996-11, Vol.31 (11), p.1645-1655
Main Authors:	Sakashita, N., Nitta, Y., Shimomura, K., Okuda, F., Shimano, H., Yamakawa, S., Tsukude, M., Arimoto, K., Baba, S., Komori, S., Kyuma, K., Yasuoka, A., Abe, H.
Format:	Article
Language:	English
Subjects:	Built-in self-test Chip scale packaging Circuit testing Clocks CMOS technology Costs Graphics Pins Random access memory Wiring
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cited_by	cdi_FETCH-LOGICAL-c291t-8002aba32263e06092dc6c16dcbae19cbc42cf05e832899ab71626d02e9e728b3
cites	cdi_FETCH-LOGICAL-c291t-8002aba32263e06092dc6c16dcbae19cbc42cf05e832899ab71626d02e9e728b3
container_end_page	1655
container_issue	11
container_start_page	1645
container_title	IEEE journal of solid-state circuits
container_volume	31
creator	Sakashita, N. Nitta, Y. Shimomura, K. Okuda, F. Shimano, H. Yamakawa, S. Tsukude, M. Arimoto, K. Baba, S. Komori, S. Kyuma, K. Yasuoka, A. Abe, H.
description	This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 /spl mu/m/sup 2/ cell and 581.8 mm/sup 2/ small die area are achieved using 0.15-/spl mu/m CMOS technology. The /spl times/61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described.
doi_str_mv	10.1109/JSSC.1996.542309
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Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 /spl mu/m/sup 2/ cell and 581.8 mm/sup 2/ small die area are achieved using 0.15-/spl mu/m CMOS technology. The /spl times/61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described.</abstract><pub>IEEE</pub><doi>10.1109/JSSC.1996.542309</doi><tpages>11</tpages></addata></record>
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source	IEEE Electronic Library (IEL) Journals
subjects	Built-in self-test Chip scale packaging Circuit testing Clocks CMOS technology Costs Graphics Pins Random access memory Wiring
title	A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture
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