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Single-event-upset (SEU) awareness in FPGA routing
The majority of configuration bits affecting a design are devoted to FPGA routing configuration. We present a SEU-aware routing algorithm that provides significant reduction in bridging faults caused by SEUs. Depending on the routing architecture switches, for MCNC benchmarks, the number of care bit...
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creator | Golshan, S. Bozorgzadeh, E. |
description | The majority of configuration bits affecting a design are devoted to FPGA routing configuration. We present a SEU-aware routing algorithm that provides significant reduction in bridging faults caused by SEUs. Depending on the routing architecture switches, for MCNC benchmarks, the number of care bits can be reduced between 13% and 19% on average with comparable delay. In addition, in Asymmetric SRAM FPGA using our router average FIT (failure-in-time) rate is reduced by 36%. |
doi_str_mv | 10.1145/1278480.1278564 |
format | conference_proceeding |
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identifier | ISSN: 0738-100X |
ispartof | 2007 44th ACM/IEEE Design Automation Conference, 2007, p.330-333 |
issn | 0738-100X |
language | eng |
recordid | cdi_ieee_primary_4261200 |
source | IEEE Xplore All Conference Series |
subjects | Algorithm design and analysis Algorithms Circuit faults Computer architecture Computer science Design Field programmable gate arrays Hardware -- Electronic design automation -- Physical design (EDA) Permission Random access memory Reliability Routing single-event-upset soft error SRAM-based FPGA Switches Testing Theory |
title | Single-event-upset (SEU) awareness in FPGA routing |
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