A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC

Although charge-redistribution successive approximation (SAR) ADCs are highly efficient, comparator noise and other effects limit the most efficient operation to below 10-b ENOB. This work introduces an oversampling, noise-shaping SAR ADC architecture that achieves 10-b ENOB with an 8-b SAR DAC arra...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2012-12, Vol.47 (12), p.2898-2904
Main Authors: Fredenburg, J. A., Flynn, M. P.
Format: Article
Language:English
Subjects:
Analog-to-digital
Applied sciences
Arrays
Capacitors
Circuit properties
CMOS
converter
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Finite impulse response filter
Frequency filters
Integrated circuits
Noise shaping
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
Switches
Transfer functions
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Description
Summary:Although charge-redistribution successive approximation (SAR) ADCs are highly efficient, comparator noise and other effects limit the most efficient operation to below 10-b ENOB. This work introduces an oversampling, noise-shaping SAR ADC architecture that achieves 10-b ENOB with an 8-b SAR DAC array. A noise-shaping scheme shapes both comparator noise and quantization noise, thereby decoupling comparator noise from ADC performance. The loop filter is comprised of a cascade of a two-tap charge-domain FIR filter and an integrator to achieve good noise shaping even with a low-quality integrator. The prototype ADC is fabricated in 65-nm CMOS and occupies a core area of 0.03 mm 2 . Operating at 90 MS/s, it consumes 806 μW from a 1.2-V supply.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2012.2217874