Search Results - Wester, Rinse

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  1. 1
    Design-time improvement using a functional approach to specify GraphSLAM with deterministic performance on an FPGA

    Design-time improvement using a functional approach to specify GraphSLAM with deterministic performance on an FPGA by Appel, Robin, Folmer, Hendrik, Kuper, Jan, Wester, Rinse, Broenink, Jan

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  2. 2
    Low-cost multi-channel underwater acoustic signal processing testbed

    Low-cost multi-channel underwater acoustic signal processing testbed by Blom, K. C. H., Wester, R., Kokkeler, A. B. J., Smit, G. J. M.

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  3. 3
    A space/time tradeoff methodology using higher-order functions

    A space/time tradeoff methodology using higher-order functions by Wester, Rinse, Kuper, Jan

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    A two step hardware design method using CλaSH

    A two step hardware design method using CλaSH by Wester, R., Baaij, C., Kuper, J.

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  5. 5
    Designing a dataflow processor using CλaSH

    Designing a dataflow processor using CλaSH by Niedermeier, A, Wester, R, Rovers, K, Baaij, C, Kuper, J, Smit, G

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