Search Results - Sparso, J.
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A Behavioral Synthesis Frontend to the Haste/TiDE Design Flow
Conference Proceeding -
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A Network Traffic Generator Model for Fast Network-on-Chip Simulation
Conference Proceeding -
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ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
Conference Proceeding -
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Current trends in high-level synthesis of asynchronous circuits
Conference Proceeding -
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A 85 /spl mu/W asynchronous filter-bank for a digital hearing aid
Conference Proceeding -
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