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Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K
by
Mariniello, Genaro
,
Barraud, Sylvain
,
Vinet, Maud
,
Cassé, Mikael
,
Faynot, Olivier
,
Calcade, Jaime
,
Antonio Pavanello, Marcelo
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Solid-state electronics
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Simulation Comparison of Self-Heating Effects in Junctionless Nanowire Transistors and FinFET Devices
by
Mariniello, Genaro
,
Pavanello, Marcelo
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ECS transactions
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Electrical characterization of stacked SOI nanowires at low temperatures
by
Rodrigues, Jaime C.
,
Mariniello, Genaro
,
Cassé, Mikael
,
Barraud, Sylvain
,
Vinet, Maud
,
Faynot, Olivier
,
Pavanello, Marcelo A.
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Solid-state electronics
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Analog characteristics of n-type vertically stacked nanowires
by
Mariniello, Genaro
,
Carvalho, Cesar Augusto Belchior de
,
Cardoso Paz, Bruna
,
Barraud, Sylvain
,
Vinet, Maud
,
Faynot, Olivier
,
Antonio Pavanello, Marcelo
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Solid-state electronics
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Evaluation of Analog Characteristics of n-Type Vertically Stacked Nanowires
by
Mariniello, Genaro
,
Barraud, Sylvain
,
Vinet, Maud
,
Faynot, Olivier
,
Paz, Bruna Cardoso
,
Pavanello, Marcelo Antonio
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Performance of Stacked SOI Nanowires in a Wide Temperature Range
by
Rodrigues, Jaime C.
,
Mariniello, Genaro
,
Casse, Mikael
,
Barraud, Sylvain
,
Vinet, Maud
,
Faynot, Olivier
,
Pavanello, Marcelo A.
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Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations
by
Mariniello, G.
,
Doria, R. T.
,
de Souza, M.
,
Pavanello, M. A.
,
Trevisoli, R. D.
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