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Search Results - Kun-Yung Ken Chang
Search Results - Kun-Yung Ken Chang
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A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface
by
Haechang Lee
,
Kun-Yung Ken Chang
,
Jung-Hoon Chun
,
Ting Wu
,
Frans, Y.
,
Leibowitz, B.
,
Nhat Nguyen
,
Chin, T.J.
,
Kaviani, K.
,
Shen, J.
,
Xudong Shi
,
Beyene, W.T.
,
Li, S.
,
Navid, R.
,
Aleksic, M.
,
Lee, F.S.
,
Quan, F.
,
Zerbe, J.
,
Perego, R.
,
Assaderaghi, F.
Published in
IEEE journal of solid-state circuits
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A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver
by
Kaviani, K.
,
Amirkhany, A.
,
Huang, C.
,
Phuong Le
,
Beyene, W. T.
,
Madden, C.
,
Saito, K.
,
Sano, K.
,
Murugan, V. I.
,
Kun-Yung Ken Chang
,
Yuan, X. C.
Published in
IEEE journal of solid-state circuits
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A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface
by
Kaviani, K.
,
Ting Wu
,
Wei, J.
,
Amirkhany, A.
,
Jie Shen
,
Chin, T. J.
,
Thakkar, C.
,
Beyene, W. T.
,
Chan, N.
,
Chen, C.
,
Bing Ren Chuang
,
Dressler, D.
,
Gadde, V. P.
,
Hekmat, M.
,
Ho, E.
,
Huang, C.
,
Phuong Le
,
Mahabaleshwara
,
Madden, C.
,
Mishra, N. K.
,
Raghavan, L.
,
Saito, K.
,
Schmitt, R.
,
Secker, D.
,
Xudong Shi
,
Fazeel, S.
,
Srinivas, G. S.
,
Zhang, S.
,
Tran, C.
,
Vaidyanath, A.
,
Vyas, K.
,
Jain, M.
,
Kun-Yung Ken Chang
,
Xingchao Yuan
Published in
IEEE journal of solid-state circuits
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A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface
by
Amirkhany, Amir
,
Wei, Jason
,
Mishra, Navin Kumar
,
Jie Shen
,
Beyene, Wendemagegnehu T.
,
Chen, Catherine
,
Chin, T. J.
,
Dressier, Deborah
,
Huang, Charlie
,
Gadde, Vijay P.
,
Hekmat, Mohammad
,
Kaviani, Kambiz
,
Hai Lan
,
Phuong Le
,
Mahabaleshwara
,
Madden, Chris
,
Mukherjee, Sanku
,
Raghavan, Leneesh
,
Saito, Keisuke
,
Secker, Dave
,
Sendhil, Arul
,
Schmitt, Ralf
,
Fazeel, Shuaeb
,
Srinivas, Gundlapalli Shanmukha
,
Ting Wu
,
Chanh Tran
,
Vaidyanath, Arun
,
Vyas, Kapil
,
Ling Yang
,
Jain, Manish
,
Chang, Kun-Yung Ken
,
Xingchao Yuan
Published in
IEEE journal of solid-state circuits
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A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs
by
Chang, K.-Y.K.
,
Wei, J.
,
Huang, C.
,
Li, S.
,
Donnelly, K.
,
Horowitz, M.
,
Yingxuan Li
,
Sidiropoulos, S.
Published in
IEEE journal of solid-state circuits
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A 50 Gb/s 32/spl times/32 CMOS crossbar chip using asymmetric serial links
by
Kun-Yung Ken Chang
,
Shang-Tse Chuang
,
McKeown, N.
,
Horowitz, M.
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Conference Proceeding
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A 2 Gb/s/pin CMOS asymmetric serial link
by
Kun-Yung Ken Chang
,
Ellersick, W.
,
Shang-Tse Chuang
,
Sidiropoulos, S.
,
Horowitz, M.
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Conference Proceeding
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A 0.4-4Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs
by
KEN CHANG, Kun-Yung
,
WEI, Jason
,
LI, Simon
,
YINGXUAN LI
,
DONNELLY, Kevin
,
HUANG, Charlie
,
SIDIROPOULOS, Stefanos
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Conference Proceeding
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