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Danger, Maxime
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Search Results - Danger, Maxime
Showing
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12
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Danger, Maxime
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1
The palaeoenvironment and settlement history of a lakeshore setting: An interdisciplinary study from the multi-layered archaeological site of Serteya II, Western Russia
by
Wieckowska-Lüth, Magdalena
,
Gauthier, Emilie
,
Thiebaut, Eva
,
Słowiński, Michał
,
Krąpiec, Marek
,
Dolbunova, Ekaterina
,
Mazurkevich, Andrey
,
Maigrot, Yolaine
,
Danger, Maxime
,
Kittel, Piotr
Published in
Journal of archaeological science, reports
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2
RSM: a small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs
by
Nassar, Maxime
,
Souissi, Youssef
,
Guilley, Sylvain
,
Danger, Jean-Luc
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3
BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation
by
Nassar, Maxime
,
Bhasin, Shivam
,
Danger, Jean-Luc
,
Duc, Guillaume
,
Guilley, Sylvain
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4
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
by
Sauvage, L.
,
Guilley, S.
,
Danger, J.-L.
,
Mathieu, Y.
,
Nassar, M.
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5
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics
by
Sauvage, Laurent
,
Nassar, Maxime
,
Guilley, Sylvain
,
Flament, Florent
,
Danger, Jean-Luc
,
Mathieu, Yves
Published in
International journal of reconfigurable computing
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6
"Re-synchronization by moments": An efficient solution to align Side-Channel traces
by
Debande, N.
,
Souissi, Y.
,
Nassar, M.
,
Guilley, S.
,
Thanh-Ha Le
,
Danger, Jean-Luc
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7
Techniques for electromagnetic attacks enhancement
by
Souissi, Youssef
,
Danger, Jean-Luc
,
Mekki, Sami
,
Guilley, Sylvain
,
Nassar, Maxime
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8
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
by
Bhasin, S.
,
Danger, J.-L.
,
Flament, F.
,
Graba, T.
,
Guilley, S.
,
Mathieu, Y.
,
Nassar, M.
,
Sauvage, L.
,
Selmane, N.
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9
Embedded systems security: An evaluation methodology against Side Channel Attacks
by
Souissi, Y.
,
Danger, J.-L
,
Guilley, S.
,
Bhasin, S.
,
Nassar, M.
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10
DPL on Stratix II FPGA: What to Expect?
by
Sauvage, L.
,
Nassar, M.
,
Guilley, S.
,
Flament, F.
,
Danger, J.-L.
,
Mathieu, Y.
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11
Place-and-route impact on the security of DPL designs in FPGAs
by
Guilley, S.
,
Chaudhuri, S.
,
Sauvage, L.
,
Graba, T.
,
Danger, J.-L.
,
Hoogvorst, P.
,
Vinh-Nga Vong
,
Nassar, M.
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12
Vade mecum on side-channels attacks and countermeasures for the designer and the evaluator
by
Guilley, S.
,
Meynard, O.
,
Nassar, M.
,
Duc, G.
,
Hoogvorst, P.
,
Maghrebi, H.
,
Elaabid, A.
,
Bhasin, S.
,
Souissi, Y.
,
Debande, N.
,
Sauvage, L.
,
Danger, J.
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12
Peer Reviewed
2
Format
Conference Proceedings
10
Articles
2
Journal Title
International Journal Of Reconfigurable Computing
1
Journal Of Archaeological Science, Reports
1
Subjects
Cryptography
8
Field Programmable Gate Arrays
7
Science & Technology
7
Technology
7
Computer Science
7
Engineering
6
Engineering, Electrical & Electronic
6
Computer Science, Hardware & Architecture
5
Differential Power Analysis
5
Telecommunications
5
Protection
4
Robustness
4
Dual-Rail With Precharge Logic
4
Page Description Languages
4
Energy Consumption
4
Automation & Control Systems
3
Field Programmable Gates Array
3
Security
3
Side-Channel Analysis
3
Side-Channel Attacks
3
Year of Publication
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To:
Source
Ieee Electronic Library (Iel) Conference Proceedings
8
Ieee Xplore All Conference Series
5
Acm Digital Library Complete
3
Sciencedirect®
1
Doaj Directory Of Open Access Journals
1
Road: Directory Of Open Access Scholarly Resources
1
Ezb Free E-Journals
1
Publicly Available Content Database
1
Open Access Journals (Hindawi Publishing)
1
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